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FPGA Verification Engineer (Fully Onsite)
Length: 2-3 months (potential extension)
Location: Santa Clara, CA 95050
*** Will have a AI based tech screen via Glider tool to Validate all skills ***
Overview:
We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team, working on state-of-the-art technologies. In this role, you will be responsible for verifying complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.
Key Responsibilities:
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Develop and maintain test benches using industry-standard verification methodologies, including UVM and SystemVerilog.
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Write, debug, and execute test cases to verify functionality, performance, and corner cases.
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Identify and troubleshoot issues in collaboration with design engineers.
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Participate in design reviews and contribute to the overall verification strategy.
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Stay current with the latest verification methodologies, tools, and best practices.
Required Skills:
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8+ years of FPGA experience.
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5+ years of experience with UVM and SystemVerilog.
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Strong understanding of FPGA, ASIC, and RTL design principles.
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Experience with Linux operating systems.
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Proficiency with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps).
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Knowledge of high-speed I/O design and protocols (e.g., PCIe, I2C, SPI).
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Hands-on experience with lab debugging tools including logic analyzers, oscilloscopes, and JTAG.
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Excellent problem-solving, debugging, and communication skills.
Desired Skills:
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Experience in hardware validation or embedded test automation.
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Familiarity with scripting languages such as Python or Perl.
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Knowledge of hardware description languages (VHDL, Verilog).
Qualifications:
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Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
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10+ years of experience in FPGA design or verification.